1. Field of the Invention
The invention relates to the field of electrically programmable MOS read-only memories.
2. Prior Art
Currently there are a number of commercially available metal-oxide-semiconductor (MOS) programmable read-only memories (PROMs), including some which may be erased. One such memory is disclosed in copending application Ser. No. 546,546, filed Feb. 3, 1975, now U.S. Pat. No. 3,938,108, "Erasable Programmable Read-Only Memory". The memory cell employed in this PROM is described in copending application Ser. No. 648,828, filed Jan. 13, 1976, now U.S. Pat. No. 3,996,657. (Both these applications are assigned to the assignee of the present application.) This memory cell includes two layers of polycrystalline silicon, one of which forms a floating gate. Electrical charge is injected into this floating gate from the substrate, thus providing the storage capacity of the cell. The memory is erased by subjecting the cells to ultraviolet radiation which neutralizes the charge stored on the floating gates.
This prior art memory, in its commercial embodiment, requires a +12 and .+-.5 volt power supplies for reading. The peripheral circuits employ level shifting for the address, data-in and data-out signals since the memory cells require a separate ground.
The invented memory also employs a double polycrystalline silicon memory cell with one layer defining a floating gate. However, the memory requires only a single (+5 volt) power supply (for reading), provides a power-down mode to conserve power and is realizable as a 16K PROM, twice the capacity of the prior art memory.